1. Field of the Invention
The present invention relates to a semiconductor structure and fabrication method thereof.
2. Description of the Related Art
For current integrated circuit development, controllers, memories, low-voltage (LV) circuits and high-voltage (HV) power devices are being integrated into a single chip, referred to as a single-chip system. For example, to handle high voltage and current, double-diffused metal oxide semiconductor (DMOS) transistors, frequently used as conventional power devices, operate with low on-resistance while sustaining high voltage. Thus, lateral double-diffused metal oxide semiconductor (LDMOS) transistors in particular, with a simple structure, are being incorporated into VLSI logic circuits.
However, the surface field of LDMOS transistors limits the voltage tolerance therein. Moreover, when operating an LDMOS device of an interdigitated structure, a high electric field occurring adjacent to the tip of a finger-shaped source results in decreased breakdown voltage of the device. Particularly, a high electric field, caused from scaling-down of related devices, decreasing device size as well as width of the source or curvature radius of the finger end, results in a very serious decrease of breakdown voltage. However, if the width of the finger shaped source is widened to enlarge the curvature radius of the finger end in order to increase the breakdown voltage and eliminate the problem mentioned above, layout flexibility of the device is sacrificed, thus hindering development for further scaling-down of related devices.
An improved semiconductor device ameliorating the disadvantages of the conventional technology is desirable.